Beyond DVFS: A First Look at Performance Under a Hardware-Enforced Power Bound

Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel’s Sandy Bridge family of processors, researchers now have what at first glance appears to be a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique as a replacement for DVFS. As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmark suite and focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the wellknown manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance. If our sample of 64 processors is representative, a cluster composed of processors at or above median efficiency would run up to 5% faster at the same power than a cluster drawn from the full distribution.